Plasma processing apparatus and control method

ABSTRACT

A plasma processing apparatus includes: a processing container; an electrode that places a workpiece thereon; a plasma generation source that supplies plasma into the processing container; a bias power supply that supplies a bias power to the electrode; an edge ring disposed at a periphery of the workpiece; a DC power supply that supplies a DC voltage to the edge ring; a controller that executes a first control procedure in which the DC voltage periodically repeats a first state having a first voltage value and a second state having a second voltage value, the first voltage value is supplied in a partial time period within each period of a potential of the electrode, and the second voltage value is supplied such that the first and second states are continuous.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority from Japanese PatentApplication Nos. 2018-191735 and 2019-156107, filed on Oct. 10, 2018 andAug. 28, 2019, respectively, with the Japan Patent Office, thedisclosures of which are incorporated herein in their entireties byreference.

TECHNICAL FIELD

The present disclosure relates to a plasma processing apparatus and acontrol method.

BACKGROUND

There is known a plasma processing apparatus capable of improving thein-plane uniformity of processing by an edge ring provided at theperiphery of a wafer placed on a stage (see, e.g., Japanese PatentLaid-Open Publication No. 2005-277369). In a plasma processingapparatus, an etching process is performed with plasma generated from agas by a radio-frequency power, so as to form fine holes or the like inthe wafer.

SUMMARY

An aspect of the present disclosure provides a plasma processingapparatus including: a processing container; an electrode configured toplace a workpiece thereon in the processing container; a plasmageneration source configured to supply plasma into the processingcontainer; a bias power supply configured to supply a bias power to theelectrode; an edge ring disposed at a periphery of the workpiece; a DCpower supply configured to supply a DC voltage to the edge ring; and acontroller configured to execute a first control procedure in which theDC voltage periodically repeats a first state having a first voltagevalue and a second state having a second voltage value higher than thefirst voltage value, the first voltage value is supplied in a partialtime period within each period of a potential of the electrode, and thesecond voltage value is supplied such that the first state and thesecond state are continuous.

The foregoing summary is illustrative only and is not intended to be inany way limiting. In addition to the illustrative aspects, embodiments,and features described above, further aspects, embodiments, and featureswill become apparent by reference to the drawings and the followingdetailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view illustrating an example of a plasma processingapparatus according to an embodiment.

FIG. 2 is a view illustrating an example of a configuration of acontroller according to the embodiment.

FIG. 3A is a view for explaining a generation of a control signalaccording to a modification of the embodiment.

FIG. 3B is a view illustrating an example where a control is performedwith a phase signal of a sensor attached to a power feeding systemaccording to the embodiment.

FIG. 3C is a view illustrating an example where a control is performedwith a signal synchronized with a period of a radio-frequency or a pulsewave of a bias power according to the embodiment.

FIG. 3D is a view illustrating an example where a control is performedwith a signal synchronized with a period of a radio-frequency or a pulsewave of a bias power according to the embodiment.

FIGS. 4A to 4C are views for explaining a relationship between a plasmapotential/a wafer potential and a sheath thickness.

FIGS. 5A to 5C are views illustrating an example of a method of applyinga negative DC voltage and effects thereof according to the embodiment.

FIG. 6 is a view illustrating an example of the method of applying anegative DC voltage according to the embodiment.

FIG. 7 is a view illustrating an example of the method of applying anegative DC voltage according to the embodiment.

FIG. 8 is a view illustrating an example of a method of applying anegative DC voltage (control of tilting) according to a modification.

FIG. 9 is a view illustrating an example of a method of applying anegative DC voltage (control of tilting) according to a modification.

FIG. 10A is a timing chart illustrating a control method according toModification 1-1 of the embodiment.

FIG. 10B is a timing chart illustrating a control method according toModification 1-2 of the embodiment.

FIG. 10C is a timing chart illustrating a control method according toModification 1-3 of the embodiment.

FIG. 10D is a timing chart illustrating a control method according toModification 1-4 of the embodiment.

FIG. 11 is a timing chart illustrating a control method according toModification 2 of the embodiment.

FIG. 12A is a timing chart illustrating a control method according toModification 3-1 of the embodiment.

FIG. 12B is a timing chart illustrating a control method according toModification 3-2 of the embodiment.

FIG. 12C is a timing chart illustrating a control method according toModification 3-3 of the embodiment.

FIG. 12D is a timing chart illustrating a control method according toModification 3-4 of the embodiment.

FIG. 13 is a view illustrating an example of a frequency of RF and apotential difference between a wafer and an edge ring according to theembodiment.

FIGS. 14A and 14B are views illustrating an example of a frequency of RFand a potential difference between a wafer and an edge ring according tothe embodiment.

FIGS. 15A to 15C are views illustrating an example of a frequency of RFand a potential difference between a wafer and an edge ring according tothe embodiment.

FIG. 16 is a timing chart illustrating a control method according toModification 4 of the embodiment.

FIG. 17 is a timing chart illustrating a control method according toModification 5 of the embodiment.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof. The illustrativeembodiments described in the detailed description, drawing, and claimsare not meant to be limiting. Other embodiments may be utilized, andother changes may be made without departing from the spirit or scope ofthe subject matter presented here.

Hereinafter, a frequency of a source power (radio-frequency) will alsobe referred to as HF (high frequency), and the source power will also bereferred to as an HF power. Further, a frequency of a bias power(radio-frequency) having a frequency lower than the frequency of thesource power will also be referred to as LF (low frequency), and thebias power will also be referred to as an LF power.

[Introduction]

Recently, the frequency of LF that is applied to the stage of the plasmaprocessing apparatus has been lowered from about 3.2 MHz to about 400kHz. Under this process condition, a problem occurs in that theroundness of the etching shape of a hole formed near the edge of asemiconductor wafer (hereinafter, also referred to as a wafer) collapsesin the radial direction, and thus, an elliptical hole with a radiallylong side is formed. Further, there is a problem in that the consumptionof the edge ring (also called a focus ring) disposed at the periphery ofthe wafer causes a tilting in which the etching shape at the edge of thewafer is formed obliquely inward.

Thus, in the plasma processing apparatus according to the presentembodiment, the problems described above are solved by making the shapeof a hole at the edge of a wafer W into a complete circle and preventingthe tilting. Hereinafter, descriptions will be made on an example of aplasma processing apparatus 1 according to the present embodiment, and acontrol of a direct current voltage (hereinafter, also referred to as a“DC voltage”) using the plasma processing apparatus 1.

[Entire Configuration of Plasma Processing Apparatus]

FIG. 1 is a view illustrating an example of the plasma processingapparatus 1 according to an embodiment. The plasma processing apparatus1 according to the present embodiment is a capacitively coupled parallelflat plate plasma processing apparatus, and includes a cylindricalprocessing container 10 made of, for example, aluminum with an anodizedsurface. The processing container 10 is grounded.

A columnar support 14 is disposed on the bottom of the processingcontainer 10 via an insulating plate 12 made of, for example, ceramics,and a stage 16 made of, for example, aluminum is provided on the support14. The stage 16 constitutes a lower electrode, and the wafer W which isan example of a target object to be processed is placed on the stage 16via an electrostatic chuck 20.

The electrostatic chuck 20 is provided on the upper surface of the stage16 to adsorb and hold the wafer W thereon by an electrostatic force. Theelectrostatic chuck 20 has a structure in which an electrode 20 a madeof a conductive film is sandwiched between insulating layers 20 b, and aDC power supply 22 is connected to the electrode 20 a. Then, the wafer Wis adsorbed and held on the electrostatic chuck 20 by an electrostaticforce such as the Coulomb force generated by a DC voltage from the DCvoltage supply 22.

A conductive edge ring 24 made of, for example, silicon is disposed atthe periphery of the wafer W on the stage 16. The edge ring 24 is alsocalled a focus ring. A cylindrical inner wall member 26 made of, forexample, quartz is provided on the lateral surfaces of the stage 16 andthe support 14.

A coolant chamber 28 is provided inside the support 14, for example, onthe circumference of the support 14. A coolant, for example, coolingwater having a predetermined temperature is supplied in a circulativemanner from a chiller unit provided outside the coolant chamber 28through pipes 30 a and 30 b, and the processing temperature of the waferW on the stage 16 is controlled by the temperature of the coolant. Inaddition, the coolant is an example of a temperature adjustment mediumthat is supplied to the pipes 30 a and 30 b in a circulative manner, andthe temperature adjustment medium may cool or heat the stage 16 and thewafer W. Further, a heat transfer gas, for example, He gas is suppliedbetween the upper surface of the electrostatic chuck 20 and the backsurface of the wafer W from a heat transfer gas supply mechanism througha gas supply line 32.

An upper electrode 34 is provided above the stage 16 to face and beparallel with the stage 16. The space between the upper electrode 34 andthe lower electrode is a plasma processing space. The upper electrode 34forms a surface that faces the wafer W on the stage 16 and is in contactwith the plasma processing space, that is, a facing surface.

The upper electrode 34 is supported on the upper portion of theprocessing container 10 via an insulating shielding member 42. The upperelectrode 34 includes an electrode plate 36 that constitutes the surfacefacing the stage 16 and is provided with a large number of gas ejectionholes 37, and an electrode support 38 that detachably supports theelectrode plate 36 and is made of a conductive material, for example,aluminum with an anodized surface. The electrode plate 36 may be made ofsilicon or SiC. A gas diffusion chamber 40 is provided inside theelectrode support 38, and a large number of gas flow holes 41 extenddownward from the gas diffusion chamber 40 to communicate with the gasejection holes 37.

In the electrode support 38, a gas inlet 62 is formed to introduce aprocessing gas into the gas diffusion chamber 40, a gas supply pipe 64is connected to the gas inlet 62, and a processing gas supply source 66is connected to the gas supply pipe 64. In the gas supply pipe 64, amass flow controller (MFC) 68 and an opening/closing valve 70 areprovided in this order from the upstream side. Then, a processing gasfor etching reaches the gas diffusion chamber 40 from the processing gassupply source 66 through the gas supply pipe 64, and is ejected into theplasma processing space from the gas ejection holes 37 in a shower formthrough the gas flow holes 41. In this manner, the upper electrode 34functions as a shower head for supplying a processing gas.

A variable DC power supply 50 is electrically connected to the edge ring24, and a DC voltage is applied from the variable DC power supply 50. Acontroller 200 controls the polarity and current/voltage of a DC voltageand a DC current supplied from the variable DC power supply 50, and anelectronic switch that turns On/Off the DC voltage and the DC current.

A first radio-frequency power supply 48 is electrically connected to thestage 16 via a power feeding rod 47 and a matching unit 46. The firstradio-frequency power supply 48 applies an LF power to the stage 16. Asa result, ions are drawn into the wafer W on the stage 16. The firstradio-frequency power supply 48 outputs a radio-frequency power having afrequency within a range of 200 kHz to 13.56 MHz. The matching unit 46matches the internal impedance of the first radio-frequency power supply48 and a load impedance with each other.

A second radio-frequency power supply 90 is connected to the stage 16via a power feeding rod 89 and a matching unit 88. The secondradio-frequency power supply 90 applies an HF power to the stage 16. Thefrequency of HF may be 13.56 MHz or more, for example, 100 MHz. Thefrequency of LF is lower than the frequency of HF and may be, forexample, 400 kHz. The matching unit 88 matches the internal impedance ofthe second radio-frequency power supply 90 and a load impedance witheach other. A filter 94 may be connected to the stage 16 to cause apredetermined radio-frequency to pass through the ground. In addition,the HF power supplied from the second radio-frequency power supply 90may be applied to the upper electrode 34.

An exhaust port 80 is provided at the bottom of the processing container10, and an exhaust device 84 is connected to the exhaust port 80 via anexhaust pipe 82. The exhaust device 84 includes a vacuum pump such as aturbo molecular pump, and is able to reduce the pressure inside theprocessing container 10 to a desired degree of vacuum. In addition, acarry-in/out port 85 is provided in the side wall of the processingcontainer 10, and is openable/closable by a gate vale 86. In addition, adeposit shield 11 is detachably provided along the inner wall of theprocessing container 10 to prevent etching by-products (deposits) fromadhering to the processing container 10. That is, the deposit shield 11constitutes the processing container wall. Further, the deposit shield11 is also provided on the outer periphery of the inner wall member 26.An exhaust plate 83 is provided between the deposit shield 11 of theprocessing container wall and the deposit shield 11 of the inner wallmember 26, at the bottom of the processing container 10. For the depositshield 11 and the exhaust plate 83, an aluminum material coated withceramics such as Y₂O₃ may be used.

When an etching process is performed in the plasma processing apparatushaving the configuration described above, first, the gate valve 86 isbrought into an open state, and the wafer W to be etched is carried intothe processing container 10 through the carry in/out port 85 and placedon the stage 16. Then, a processing gas for etching is supplied from theprocessing gas supply source 66 to the gas diffusion chamber 40 at apredetermined flow rate, and supplied into the processing container 10through the gas flow holes 41 and the gas ejection holes 37. Further,the inside of the processing container 10 is exhausted by the exhaustdevice 84, such that the pressure inside the processing container 10becomes a set value within a range of, for example, 0.1 Pa to 150 Pa.Here, various gases that are used in related arts may be employed as theprocessing gas, and for example, a gas containing a halogen elementwhich is a fluorocarbon gas (C_(x)F_(y)) such as C₄F₈ gas as arepresentative example may be appropriately used. In addition, othergases such as Ar gas and O₂ gas may be contained.

As described above, in a state where the etching gas is introduced intothe processing container 10, a HF power is applied to the stage 16 fromthe second radio-frequency power supply 90. Further, a LF power isapplied to the stage 16 from the first radio-frequency power supply 48.Further, a DC voltage is applied to the electrode 20 a from the DC powersupply 22, and the wafer W is held on the stage 16. Further, a negativeDC voltage is applied to the edge ring 24 from the variable DC powersupply 50.

The processing gas ejected from the gas ejection holes 37 of the upperelectrode 34 is dissociated and ionized mainly by the HF power, so thatplasma is generated. The processing target surface of the wafer W isetched by radicals or ions in the plasma. In addition, by applying theLF power to the stage 16, it is possible to broaden a plasma controlmargin such as controlling ions in plasma and enabling etching of holeswith a high aspect ratio.

The plasma processing apparatus 1 is provided with the controller 200that controls the operation of the entire apparatus. The controller 200executes desired plasma processing such as etching, according to arecipe stored in a memory such as a read only memory (ROM) or a randomaccess memory (RAM). In the recipe, for example, process time, apressure (exhaust of gas), a radio-frequency power or voltage, flowrates of various gases, the temperature inside the processing container(e.g., the temperature of the upper electrode, the temperature of theside wall of the processing container, the temperature of the wafer W orthe temperature of the electrostatic chuck), and the temperature of thecoolant output from the chiller unit are set as control information ofthe apparatus for process conditions. In addition, the recipe thatrepresents the programs or process conditions may be stored in a harddisk or a semiconductor memory. In addition, the recipe may be set at apredetermined position in a state of being stored in a portablecomputer-readable storage medium such as a CD-ROM or a DVD, and may beread out.

For example, the controller 200 may perform a control to apply thenegative DC voltage output from the variable DC power supply 50 in apartial time period within each period of a voltage, current orelectromagnetic field measured in a transmission path of the bias power,a variance of light emission of generated plasma, or a variance ofsheath thickness of plasma above the wafer W (the lower electrode)(hereinafter, also referred to as a “periodically varying parameter”),and to alternately repeat the On/Off of the negative DC voltage. Thecontroller 200 may perform a control to apply the voltage of HF outputfrom the second radio-frequency power supply 90 in a partial time periodwithin each period of the periodically varying parameter, and toalternately repeat the On/Off of the voltage of HF. As a result, theshape of a hole at the edge of the wafer W may be made in a completecircle, and the tilting may be prevented.

The transmission path of the bias power refers to the firstradio-frequency power supply 48→the matching unit 46→the power feedingrod 47→the stage 16→plasma→the upper electrode 34→(ground). The voltage,current or electromagnetic field measured in the transmission path ofthe bias power refers to a voltage, current or electromagnetic fieldmeasured in the portion from the first radio-frequency power supply 48to the stage 16 via the inside of the matching unit 46 and the powerfeeding rod 47, and in the upper electrode 34, or an electromagneticfield measured with plasma.

The negative DC voltage is controlled such that a first state and asecond state to be described later are periodically repeated, the firststate is applied in a partial time period within each period of theperiodically varying parameter, and the second state is appliedcontinuously with the first state.

The periodically varying parameter may be any one of a voltage, current,and electromagnetic field measured in any one of the members from thestage 16 to the inside of the matching unit connected via the powerfeeding rod 47.

The On/Off of the DC voltage or High/Low of an absolute value of the DCvoltage may be controlled to be synchronized with a signal synchronizedwith the period of the radio-frequency or pulse wave of the bias power,or a phase within one period of any one of a voltage, current, and anelectromagnetic field measured in the transmission path of the biaspower (power feeding system). For example, the controller 200 maycontrol the On/Off or High/Low of the DC voltage to be synchronized withthe phase within one period of a voltage or current of LF.

In addition, the state of the signal synchronized with the period of theradio-frequency or pulse wave of the bias power, or any one of thevoltage, current, and electromagnetic field measured in the powerfeeding system of the bias power will also be referred to as a“reference electrical state.” The DC voltage may be controlled such thatthe first state and the second state to be described later arealternately applied in synchronization with the phase within one periodof the reference electrical state.

As the method of measuring the periodically varying parameter in thetransmission path of the bias power, there is, for example, a method ofinstalling a voltage sensor, a current sensor or a BZ sensor (a sensorfor measuring an induced magnetic field) near any one portion of thetransmission path of the bias power, and measuring a voltage, current orinduced magnetic field of each portion. In addition, while FIG. 2illustrates a voltage sensor 300, the sensor is not limited thereto andmay be a current sensor or a BZ sensor. In addition, each sensordescribed above may be connected to the power feeding rod 47, but thearrangement of each sensor is not limited thereto. A signal from thesensor such as the voltage sensor 300 is input to, for example, a signalgeneration circuit 102 of the controller 200.

In addition, the period of light emission of plasma and the period ofthe variance of sheath thickness of plasma above the wafer W may be usedas indexes. The period of light emission of plasma may be detected by,for example, a photodiode- or photomicro-sensor. As for the sheaththickness, the variance of sheath thickness may be measured by using,for example, an ICCD camera and clicking the shutter of the camera at aninterval of nanoseconds (e.g., 10 nsec to 250 nsec).

In addition, the stage 16 is an example of an electrode for placing thewafer W thereon (the lower electrode). The upper electrode is an exampleof an electrode that faces the lower electrode. The firstradio-frequency power supply 48 is an example of a bias power supplythat supplies a bias power to the lower electrode. The secondradio-frequency power supply 90 is an example of a source power supplythat supplies a source power having a frequency higher than the biaspower, to the lower electrode or the upper electrode. The variable DCpower supply 50 is an example of a DC power supply that supplies a DCvoltage to the edge ring 24. The source power supply corresponds to aplasma generation source that supplies plasma into the processingcontainer 10.

The controller 200 is an example of a controller that controls the biaspower supply, the source power supply, and the DC power supply. Thepotential of the lower electrode (the stage 16) to which the bias poweris applied will also be referred to as an electrode potential.

[Configuration of Controller]

The specific configuration of the controller 200 will be described withreference to FIG. 2. The controller 200 includes a processor 100, thesignal generation circuit 102, directional couplers 105 and 108, a powermeter 111, and an oscilloscope 112. However, the power meter 111, theoscilloscope 112, and the directional coupler 108 may not be provided.

In the power feeding line of the first radio-frequency power supply 48,the directional coupler 105 is connected between the firstradio-frequency power supply 48 and the matching unit 46. In the powerfeeding line of the second radio-frequency power supply 90, thedirectional coupler 108 is connected between the second radio-frequencypower supply 90 and the matching unit 88.

The directional coupler 105 gives a portion of a traveling wave power ofLF to the oscilloscope 112. The directional coupler 108 gives a portionof a traveling wave power of HF to the oscilloscope 112. In anembodiment, the frequency of LF displayed on the oscilloscope 112 is,for example, 400 kHz, and the frequency of HF displayed on theoscilloscope 112 is, for example, 100 MHz. Accordingly, in theoscilloscope 112, the waveform of the traveling wave of LF and thewaveform of the traveling wave of HF may be observed.

The directional coupler 108 gives a portion of the traveling wave of HFto the power meter 111. The power meter 111 measures the electric energyof the traveling wave of HF.

The directional coupler 105 gives a portion of the traveling wave of LFto the processor 100. The processor 100 creates a DC synchronizationsignal to be synchronized with the traveling wave of LF. For example,the processor 100 may create the DC synchronization signal insynchronization with a positive timing of the traveling wave of LF. Inaddition, instead of the directional coupler 105, the waveform of LFdetected by the sensor described above may be given to the processor100.

The processor 100 gives the created synchronization signal to the signalgeneration circuit 102. The signal generation circuit 102 generates acontrol signal that is synchronized with the traveling wave of LF fromthe given synchronization signal, and gives the generated control signalto the variable DC power supply 50 and the first radio-frequency powersupply 48.

There are two methods for generating the control signal as follows. In acase where the first radio-frequency power supply 48 is a general powersupply, the directional coupler 105 takes out a portion of the LF poweroutput from the first radio-frequency power supply 48 as a waveform, andinputs the waveform to the processor 100. However, the presentdisclosure is not limited thereto, and the processor 100 may directlyinput a portion of the LF power from the first radio-frequency powersupply 48. The processor 100 creates an ON signal in synchronizationwith the signal of the input waveform or having an arbitrary delay andan arbitrary width from the signal of the input waveform, and transmitsthe ON signal to the signal generation circuit 102. The processor 100may directly generate a signal of LF for controlling the firstradio-frequency power supply 48 and create an ON signal insynchronization with the signal of LF or having an arbitrary delay andan arbitrary width from the signal of LF, without inputting a portion ofthe LF power from the first radio-frequency power supply 48. The ONsignal is an example of a synchronization signal.

The signal generation circuit 102 sends a command signal to the variableDC power supply 50 in order to generate the DC voltage during the ONsignal. As the command signal, a control signal for generating the DCvoltage during the ON signal or the ON signal itself is used accordingto the input form of the variable DC power supply 50. Similarly, thesignal generation circuit 102 may send a command signal to the secondradio-frequency power supply 90 in order to generate the HF power duringthe ON signal.

In a case where the first radio-frequency power supply 48 is anamplifier that amplifies the LF power, voltage or current, the signalgeneration circuit 102 may take out a portion of the LF output from thefirst radio-frequency power supply 48 as a waveform, and create an ONsignal having an arbitrary delay and an arbitrary width from the signalof the waveform, rather than using the signal from the directionalcoupler 105. The signal generation circuit 102 transmits the signal ofthe waveform and the ON signal to the variable DC power supply 50.

For example, instead of the variable DC power supply 50, an AC powersupply (not illustrated) may be provided and electrically connected tothe edge ring 24, such that a radio-frequency voltage may be appliedfrom the AC power supply to the edge ring 24 based on a control (ON)signal. The variable DC power supply 50 or the AC power supply is anexample of a power supply that supplies at least one of a negative DCvoltage and a radio-frequency voltage to the edge ring 24.

In addition, as illustrated in FIG. 3A, a portion of LF output from thefirst radio-frequency power supply 48 may be input to a phase shiftcircuit 210 provided in the controller 200, and a radio-frequencyvoltage obtained by shifting the phase of LF by a predetermined amountwith the phase shift circuit 210 may be applied to the edge ring 24.

Instead of shifting the phase of LF by a predetermined amount with thephase shift circuit 210, a radio-frequency voltage having an arbitrarydelay and an arbitrary width may be generated from the waveform of LFoutput from the first radio-frequency power supply 48, and the generatedradio-frequency voltage may be applied to the edge ring 24.

However, the above-described method of generating a control signal is anexample, and the present disclosure is not limited thereto. Withoutbeing limited to the circuit of the controller 200 illustrated in FIG.2, another hardware or software may be used as long as the hardware orsoftware is capable of generating a control signal for applying at leastone of the negative DC voltage and the radio-frequency voltage in apartial time period within each period of the given periodically varyingparameter. In a case of the DC voltage, for example, a control signalfor alternately repeating the On/Off of the DC voltage may be generated.

The amplifier of the first radio-frequency power supply 48 amplifies theamplitude of a modulation signal (amplitude modulation (AM)) of LF of400 kHz, and supplies the LF to the lower electrode. The amplifier ofthe second radio-frequency power supply 90 amplifies the amplitude of amodulation signal of HF of 100 MHz, and supplies the HF to the lowerelectrode.

From the given synchronization signal, the signal generation circuit 102may generate a control signal for applying the negative DC voltage in apartial time period within each period of the periodically varyingparameter measured in the transmission path of the bias power andcontrolling the absolute value of the negative DC voltage to bealternately repeated between High and Low, and may give the generatedcontrol signal to the variable DC power supply 50. From the givensynchronization signal, the signal generation circuit 102 may generate acontrol signal for applying the radio-frequency voltage in a partialtime period within each period of the periodically varying parametermeasured in the transmission path of the bias power and controlling theradio-frequency voltage to be alternately repeated between High and Low,and may give the generated control signal to the second radio-frequencypower supply 90.

For example, FIGS. 3B and 3C are examples where any one of a voltage,current, and electromagnetic field measured in the transmission path ofthe bias power (power feeding system) is set as the “referenceelectrical state.” For example, in FIG. 3B, the processor 100 inputs anyone of a voltage or current of HF, a voltage or current of LF, a phasesignal of HF, and a phase signal of LF from a sensor such as a VI probeattached to the transmission path. The processor 100 alternately appliesthe first state and the second state of the DC voltage insynchronization with the phase within one period of the referenceelectrical state that represents the input voltage or current of HF,voltage or current of LF, phase signal of HF, or phase signal of LF.

The processor 100 may generate a signal synchronized with the period ofthe radio-frequency or pulse wave of the bias power output from thefirst radio-frequency power supply 48, rather than using the signal fromthe sensor. In this case, the state of the generated signal may be setas the reference electrical state. Further, the process of measuring thereference electrical state in the power feeding system of the bias powermay be omitted. For example, in FIG. 3C, the processor 100 inputs aphase signal of LF (low power waveform) or a signal related toinformation of the bias power from the first radio-frequency powersupply 48, and generates a signal synchronized with the period of theradio-frequency or pulse wave of the bias power based on the inputsignal. The processor 100 outputs the generated signal to the variableDC power supply 50. Based on this signal, the variable DC power supply50 alternately applies the first state and the second state of thesource power.

In addition, as illustrated in FIG. 3D, the processor 100 may generate asignal for controlling the first radio-frequency power supply 48 andgenerate a signal synchronized with the generated signal, so as togenerate a signal synchronized with the period of the radio-frequency orpulse wave of the bias power output from the first radio-frequency powersupply 48, rather than using the signal from the first radio-frequencypower supply 48. In this case, the processor 100 not only generates thesignal of LF for controlling the first radio-frequency power supply 48(see, e.g., FIG. 5A), but also generates the signal of the DC voltagesignal synchronized with the generated signal as illustrated in, forexample, FIG. 5A. The processor 100 transmits the generated signal of LFto the first radio-frequency power supply 48, and transmits thegenerated signal of the DC voltage to the variable DC power supply 50.The first radio-frequency power supply 48 outputs the bias power basedon the signal of LE The variable DC power supply 50 alternately appliesthe first state and the second state of the DC voltage based on thesignal of the DC voltage. The generated signal of LF and the generatedsignal of the DC voltage include power information.

[Plasma Potential/Wafer Potential and Sheath Thickness]

FIGS. 4A to 4C are views for explaining a relationship between a plasmapotential/a wafer potential and a sheath thickness. The wafer potentialis substantially the same as the electrode potential. In FIG. 4A, thehorizontal axis represents time, and the vertical axis represents thepotential of the wafer W. FIGS. 4A to 4C represent a result obtained byactually measuring the potential of the wafer W when an HF power with afrequency of 100 MHz and an LF power with a frequency of 400 kHz areapplied to the stage 16. The potential of the wafer W is basicallyrepresented by the amplitude of LF Vpp of the low frequency of 400 kHzas indicated by the line “a,” and vibrates with the width of HF Vppindicated by the line “b” when the HF power with the radio-frequency of100 MHz is superimposed on the LF power.

The plasma potential is slightly higher than the highest potential inthe processing container 10. The potential of the wafer is determinedmainly by the LF of the low frequency, in the LF and the HF that aresuperimposed and applied to the stage 16, and it may be understood thatthe potential difference between the plasma potential and the wafer Wpotential becomes small in or in the vicinity of the region where thewafer W potential has a positive phase, that is, the potential of thewafer W is positive as indicated by the region A, and becomes very largein the region where the wafer W potential is negatively large, that is,the potential of the wafer W is negatively deep as indicated by theregion B.

The sheath thickness is obtained by Equation (1) and is substantiallyproportional to the potential difference between the plasma potentialand the wafer W potential.

$\begin{matrix}{{{Sheath}\mspace{14mu}{Thickness}} = {\frac{\sqrt{2}}{3}\left( \frac{ɛ_{0} \cdot {Te}}{e \cdot {Ne}} \right)\left( \frac{2V_{dc}}{Te} \right)^{\frac{3}{4}}}} & \left\lbrack {{Equation}\mspace{14mu} 1} \right\rbrack\end{matrix}$

Here, Vdc is a self-bias, Te is a plasma temperature, Ne is a plasmadensity, ε0 is a dielectric constant of vacuum, and “e” is an elementaryelectrical charge.

Thus, when the wafer W potential has a positive phase, the potentialdifference between the plasma potential and the wafer W potential andthe potential difference between the plasma potential and the potentialof the edge ring 24 become small, and the thickness of sheath above thewafer W and the edge ring 24 becomes thin as illustrated in FIG. 4B.

As a result, plasma enters a gap S formed between the edge of the waferW and the edge ring 24, and a distortion occurs in the sheath. Thus, inthe gap S, ions close to the outer periphery of the wafer W are incidentobliquely toward the inner side of the wafer W at the edge of the waferW due to the distortion of sheath.

Meanwhile, when the wafer W potential has a negatively large phase, thatis, in the region B, the potential difference between the plasmapotential and the wafer W potential and the potential difference betweenthe plasma potential and the potential of the edge ring 24 become large,and the thickness of sheath above the wafer W and the edge ring 24becomes thick as illustrated in FIG. 4C.

Accordingly, when the wafer W potential has a negatively large phase,the distortion of sheath does not occur in the gap S, and ions aresufficiently accelerated in the sheath and are vertically incident onthe wafer W at the edge of the wafer W as well.

As described above, at the edge of the wafer W, since thepresence/absence of the distortion of sheath in the gap S areperiodically repeated, the oblique incidence of ions and the verticalincidence of ions on the wafer W are periodically and continuouslyrepeated according to the wafer W potential, and as a result, it isbelieved that a hole at the edge of the wafer W is formed in anelliptical shape.

In the meantime, the distortion of sheath does not occur when no gap Sexists. However, wafers W are carried one by one, and the position ofeach wafer W is slightly shifted each time the wafer W is placed on thestage 16. Accordingly, the gap S needs to be provided between the waferW and the edge ring 24, so as to prevent the wafer W from being incontact with the edge ring 24 even when the position of the wafer W isshifted.

In addition, in recent years, the LF has been lowered from several MHzto several hundred kHz, and actually, the roundness of a hole collapsesor tilting occurs at the edge of the wafer W. That is, when the LF isabout several MHz, ions are heavy even though the sheath thicknessvaries according to the period of the LF. Hence, the accelerationdirection of ions is not clearly distinguished, the ions are incidentwith substantially constant energy due to the self-bias Vdc of the LF,and the incidence angle of the ions changes less.

Meanwhile, for example, when the LF is as low as several hundred kHz,the acceleration direction of ions is clearly distinguished at a timingwhen the sheath is thick and at a timing when the sheath is thin, thechange of the incidence angle of ions is periodically and continuouslyrepeated when the wafer potential or electrode potential is positive andwhen the wafer potential or electrode potential is negative, and a holeat the edge of the wafer W is easily formed in an elliptical shape.

Thus, in the plasma processing apparatus 1 according to the presentembodiment, the negative DC voltage is applied to the edge ring 24according to the wafer potential or electrode potential, and thethickness of sheath in the edge ring 24 is controlled. As a result, ahole with high roundness is formed in the wafer W, and the occurrence oftilting is prevented so that the etching shape may become vertical.

[Method of Applying Negative DC Voltage and Effects Thereof]

Descriptions will be made on a method of applying the negative DCvoltage and effects thereof according to the present embodiment withreference to FIGS. 5A to 5C. FIGS. 5A to 5C are views illustrating anexample of the method of applying the negative DC voltage according tothe embodiment, and an example of effects thereof. In FIG. 5A, thehorizontal axis represents time, and the vertical axis represents thepotential of the wafer W. FIGS. 5A to 5C, 6, and 8 illustrate that HF issuperimposed on LF which has a deep Vdc and vibrates with large Vpp, andthe HF vibrates with small Vpp.

The controller 200 controls the negative DC voltage to be applied to theedge ring 24 according to a timing when the electrode potential ispositive. Hereinafter, the control of the DC voltage to be applied tothe edge ring 24 will be described.

As an example of the method of controlling the DC voltage to be appliedto the edge ring 24, the controller 200 may apply the negative DCvoltage to the edge ring 24 in synchronization with a timing when theelectrode potential is positive. In addition, the controller 200 mayapply the negative DC voltage to the edge ring 24 at a timing when theelectrode potential is around zero. In addition, the controller 200 mayapply the negative DC voltage to the edge ring 24 at a timing when theelectrode potential is closer to zero than the self-bias Vdc. Inaddition, the controller 200 may apply the negative DC voltage to theedge ring 24 at a timing other than a time zone when the electrodepotential is negatively deepest. In addition, the controller 200 maycontrol the negative DC voltage such that plasma does not enter the gapS between the periphery of the wafer W and the edge ring 24 or a hole isformed in a complete circle by empirical rules.

The sheath becomes thin when the electrode potential is positive.Accordingly, at this time, by applying the negative DC voltage (e.g., aDC voltage d1 represented in the region A of FIG. 5A) to the edge ring24, the potential of the edge ring 24 is controlled to the potentialindicated by the line “c” in FIG. 5A. As a result, at the timing of theregion A where the potential difference between the wafer W potentialand the plasma potential is small, the potential difference increases sothat the sheath above the edge ring 24 may be made thick. That is, byapplying the negative DC voltage when the electrode potential ispositive or nearly positive, the sheath thickness may be increased fromthe state illustrated in FIG. 5B to the state illustrated in FIG. 5C. Asa result, it is possible to avoid that plasma enters the gap S of theperiphery of the wafer W. As a result, it is possible to avoid that ionsare obliquely incident on the wafer W at the edge of the wafer W due tothe distortion of sheath in the gap S, and it is possible to prevent ahole from being formed in an elliptical shape or prevent the occurrenceof tilting.

However, the timing for applying the negative DC voltage is not limitedto the timing when the electrode potential is positive. The negative DCvoltage may be applied at other timings, for example, a timing when theelectrode potential includes a positive peak, a timing that includes thetiming when the electrode potential is positive and negative timings ofthe electrode potential before and after the timing when the electrodepotential is positive, a timing other than a timing when the electrodepotential is around zero or a timing when the electrode potential isdeeper than the self-bias Vdc, and a time having an arbitrary delay andan arbitrary width from a timing when the electrode potential ispositive or negative.

In addition, as the means for increasing the sheath thickness, insteadof continuously applying the negative DC voltage, the timing forsupplying the negative DC voltage or the like may be controlledaccording to a pulse-type power corresponding to the peak of the LFvoltage (hereinafter, also referred to as an “LF pulse”). Additionally,the HF power may be controlled to increase.

FIG. 7 illustrates a method of controlling the negative DC voltage to beapplied to the edge ring 24 according to an LF pulse “i.” For example,as illustrated in FIG. 7, the negative DC voltage to be applied to theedge ring 24 may be controlled according to the LF pulse “i” having aduty of 30% to 50%. For example, when the LF pulse “i” is 0, thenegative DC voltage may be applied to the edge ring 24, and when the LFpulse “i” is not 0, applying the negative DC voltage may be stopped, thenegative DC voltage may still be continuously applied, or the negativeDC voltage may be applied to reach the voltage of LF Vpp indicated bythe curve “c” illustrated in FIG. 7.

As a result, the sheath may be controlled to become thick even in theregion A where the sheath above the wafer W is thin, so that a hole withhigh roundness may be formed at the edge of the wafer W as well, theoccurrence of tilting may be prevented, and thus, the etching shape maybecome vertical. In addition, the negative LF pulse “i” having the dutyof 30% to 50% refers to a waveform in which the ratio of time when thevoltage is zero is 30% to 50% in one period.

While the negative DC voltage may be continuously applied to the edgering 24, applying the negative DC voltage to the edge ring 24 may beturned On/Off. In this case, as an example of a condition, when a DCpower supply is capable of carrying current only in one direction in onequadrant or when a diode or the like is attached to the output of a DCpower supply such that current is carried only in one direction, anegative DC voltage e1 may be applied at a timing when it is desired tomake the wafer potential negatively larger than the plasma potential,and a DC voltage e2 may be controlled to zero at the other timings, asillustrated in FIG. 6. As for the negative DC voltage applied in thismanner, the first voltage value e1 of the first state is smaller thanthe second voltage value e2 of the second state.

In addition, in a case where a power supply is capable of carryingcurrent only in one direction, current does not flow even when anegative DC voltage with a potential shallower than the plasma potentialis applied, and the effect in making the sheath thick is not obtained.In a case where a power supply is a four quadrant power supply, thedirection of each of voltage and current is bidirectional, and thus, theDC voltage may be applied according to the wafer W potential withoutcutting off the DC voltage, in order to protect the power supply. Asillustrated in FIG. 5A, the negative DC voltage d1 may be applied at atiming when it is desired to make the wafer potential negatively largerthan the plasma potential, and a negative DC voltage d2 may be appliedat the other timings to reach the voltage of LF Vpp of the curve “a”illustrated in FIG. 5A. In this case as well, as for the appliednegative DC voltage, the first voltage value d2 of the first state issmaller than the second voltage value d1 of the second state.

(Other Examples of Method of Applying Negative DC Voltage)

The thickness of sheath above the wafer W may be measured, and the valueof the negative DC voltage to be applied to the edge ring 24 may becontrolled according to the measured thickness of sheath. For example,the negative DC voltage may be applied to the edge ring 24 when thethickness of sheath above the wafer W is equal to or less than apredetermined threshold value. The supply of the negative DC voltage tothe edge ring 24 may be stopped when the thickness of sheath above thewafer W exceeds the threshold value.

In addition, when the thickness of sheath above the wafer W is equal toor less than the threshold value, the negative DC voltage to be appliedto the edge ring 24 may be controlled to vary by stages or smoothly.

The negative DC voltage may be applied to the edge ring 24 in a timezone having an arbitrary delay and an arbitrary width from the timingwhen the electrode potential is positive. For example, the negative DCvoltage may be applied to the edge ring 24 in a time zone that is aslong as a predetermined time before and after the timing when theelectrode potential is positive, or in a time zone that is as short as apredetermined time before and after the timing when the electrodepotential is positive.

The DC voltage is controlled by the controller 200 using a storagemedium having a program for periodically repeating the first statehaving the first voltage value and the second state having the secondvoltage value higher than the first voltage value, applying the firstvoltage value in a partial time period within each period of theelectrode potential, and controlling the second voltage value such thatthe first state and the second state are continuous.

[Modifications: Method of Applying DC Voltage (Control of Tilting)]

Next, descriptions will be made on a method of applying the negative DCvoltage depending on the consumption of the edge ring 24, according to amodification with reference to FIGS. 8 and 9.

When a stepped difference occurs between the height of sheath of thewafer W and the height of sheath of the edge ring 24 due to theconsumption of the edge ring 24, the etching shape at the edge of thewafer W does not become vertical and becomes oblique causing a tilting.In this regard, the sheath may be made thick by increasing the absolutevalue of the negative DC voltage to be applied to the edge ring 24according to the consumption of the edge ring 24.

That is, in the method of applying the DC voltage to the edge ring 24according to the modification, the negative DC voltage controlled by themethod of applying the DC voltage according to the embodiment describedabove is corrected such that the absolute value of the negative DCvoltage increases according to the degree of consumption of the edgering 24, and the corrected negative DC voltage is applied to the edgering 24. As a result, as illustrated in FIG. 8, the potential of theedge ring 24 after the DC voltage is applied may be changed from apotential “c” when the uncorrected negative DC voltage is applied, to apotential “f” when the negative DC voltage corrected according to thedegree of consumption of the edge ring 24 is applied.

As a result, the thickness of sheath of the edge ring 24 is made thickaccording to the consumption of the edge ring 24, so that the thicknessof sheath of the wafer W and the thickness of sheath of the edge ring 24may be aligned. As a result, it is possible to suppress the occurrenceof tilting and form a hole in a complete circle at the edge portion ofthe wafer W.

The controller 200 may independently correct the DC voltage in each ofthe case where the electrode potential is positive and the case wherethe electrode potential is negative. For example, the controller 200 maycorrect the DC voltage to be applied, to different negative values forthe cases where the electrode potential is positive and negative, or mayturn Off the negative DC voltage when the electrode potential isnegative.

The controller 200 may correct the negative DC voltage to be controlled,by predicting the degree of consumption of the edge ring 24 based on atleast one of the use time of the edge ring 24, the application time ofthe HF power, and the total application time of the HF power and LFpower.

As the correcting method, for example, a DC voltage correction value forthe use time of the edge ring 24, the application time of the HF power,or the total application time of the HF power and the LF power may bestored in advance in the memory of the controller 200. From theinformation stored in the memory, the controller 200 may extract a DCvoltage correction amount corresponding to the consumption amount of theedge ring 24 based on the use time of the edge ring 24, the applicationtime of the HF power, or the total application time of the HF power andthe LF power, and determine a corrected DC voltage value to be appliedto the edge ring 24.

Alternatively, a DC voltage correction value for the consumption amountof the edge ring 24 is stored in advance in the memory of the controller200. The controller 200 may measure the actual thickness of the edgering 24, extract a DC voltage correction amount corresponding to theconsumption amount of the edge ring 24 based on the actual measurementvalue of the consumption amount of the edge ring 24 from the informationstored in the memory, and determine a corrected DC voltage value to beapplied to the edge ring 24.

The negative DC voltage may be controlled in multiple stages accordingto the electrode potential. FIG. 9 represents an example where a fixedor variable negative DC voltage is applied according to the electrodepotential in each stage. In FIG. 9, three-stage different fixed DCvoltages are applied according to the electrode potential (waferpotential). The “g” represents an example where the three-stage negativeDC voltages are applied by stages to the edge ring 24. The negative DCvoltages may be smoothly applied to the edge ring 24 according to theelectrode potential.

As described above, according to the plasma processing apparatus 1 andthe DC applying method in the present embodiment, the timing forapplying the DC voltage or the like is controlled according to theelectrode potential, so that it is possible to suppress the formation ofa hole in an elliptical shape or the occurrence of tilting at the edgeof the wafer W.

[Control Method]

As described above, the control method of the parallel flat plate typeplasma processing apparatus 1 according to the embodiment includes aprocess of supplying the bias power to the stage 16 on which the wafer Wis placed, and a process of supplying the negative DC voltage to theedge ring 24, and a process of supplying the source power to the plasmaprocessing space.

In this control method, the negative DC voltage or the radio-frequencyvoltage periodically repeats the first state and the second state. Asfor the negative DC voltage, the first voltage value of the first stateis smaller than the second voltage value of the second state. As for theradio-frequency voltage, the first voltage value of the first state islarger than the second voltage value of the second state.

Further, the present control method includes a first control process ofapplying the first state in a partial time period within each period ofthe periodically varying parameter measured in the transmission path ofthe bias power, and applying the second state continuously with thefirst state.

The first state and the second state are not limited to the state wherethe DC voltage to be applied to the edge ring is controlled in theOn/Off manner, and includes a state where the absolute value of thevoltage value is controlled to High/Low.

Modifications 1-1 to 1-4

Next, descriptions will be made on a control method of the plasmaprocessing apparatus 1 according to Modifications 1-1 to 1-4 of theembodiment. In Modifications 1-1 to 1-4, a control is performed tointermittently stop any one or both of the bias power and the DCvoltage. FIGS. 10A to 10D are timing charts illustrating the controlmethod according to Modifications 1-1 to 1-4 of the embodiment.

Modification 1-1 of FIG. 10A includes a second control process ofintermittently stopping the DC voltage in an independent period from theperiod of the periodically varying parameter that is represented by theLF voltage as an example, in addition to the first control process. Thefirst control process and the second control process are repeatedlyperformed.

In Modification 1-1, the LF voltage is applied in the same period in thefirst control process and the second control process. Meanwhile, as forthe DC voltage, the first state and the second state are alternatelyrepeated one or more times in the first control process, andintermittently stopped in the second control process, that is, betweenfirst control processes.

In the first control process and the second control process, thefrequency of LF may be, for example, 0.1 Hz to 100 kHz. In Modification1-1 of FIG. 10A to Modification 1-4 of FIG. 10D, the DC voltage or theradio-frequency voltage is applied in a partial time period when theperiodically varying parameter that is the electrode potential as anexample includes a positive value, such that the potential of the edgering becomes the first state, and the second state is appliedcontinuously with the first state. The DC voltage is a negative value,and the first voltage value of the first state is smaller than thesecond voltage value of the second state.

In Modification 1-1 of FIG. 10A to Modification 1-4 of FIG. 10D, thefirst state of the DC voltage has a negative voltage value, and thesecond state is zero. In addition, the duty ratio of the DC voltage(=fourth state/(third state+fourth state)) may fall in a range of 1% to99%.

A predetermined radio-frequency voltage (hereinafter, also referred toas an “RF voltage”) may be supplied to the edge ring 24. In this case,the RF voltage may be supplied from the second radio-frequency powersupply 90 to the edge ring 24, or an RF power supply may be separatelyprovided in the stage 16 to apply the RF voltage. As for the RF voltage,the first voltage value of the first state is larger than the secondvoltage value of the second state.

In Modification 1-1 of FIG. 10A, the state where the DC voltagesynchronized with the timing when the LF voltage is positive takes thefirst state in the first control process is an example of a third state.The state of the DC voltage that is independent from the period of theLF voltage in the second control process is an example of a fourth statewhich is different from the third state.

The control method according to Modification 1-2 of FIG. 10B includes athird control process of intermittently stopping the bias power (the LFvoltage) in an independent period from the period of the DC voltage, inaddition to the first control process which is the same as Modification1-1. In the third control process, the state of the bias power is anexample of the fourth state.

In Modification 1-2, the first control process and the third controlprocess are repeatedly performed. In Modification 1-2, as for the DCvoltage in the third control process, the first state and the secondstate are repeated in the same period as that in the first controlprocess.

In addition, in the first control process, the frequency of LF may be,for example, 0.1 Hz to 100 Hz, and the duty ratio of the LF voltage(=fourth state/(third state+fourth state)) may fall in the range of 1%to 90%.

In the control method according to Modification 1-3 of FIG. 10C, thecontrol of DC in the second control process of Modification 1-1 and thecontrol of LF in the third control process of Modification 1-2 areperformed, in addition to the first control process which is the same asModification 1-1. That is, in Modification 1-3, the state where both theDC voltage and the bias power are intermittently stopped is an exampleof the fourth state.

The period for intermittently stopping the bias power and the period forintermittently stopping the DC voltage may be synchronized with eachother. In this case, the periods for intermittently stopping the DC andthe bias power may be the same as illustrated in FIG. 10C, or the DC maybe shifted behind or in front of the bias power as illustrated in FIG.10D.

In addition, in the third state of FIGS. 10A to 10D, the DC voltage isturned On at the partial timing when the bias power is positive.However, the present disclosure is not limited thereto. In addition,instead of periodically turning On/Off the DC voltage, the DC voltagemay be controlled such that the absolute value of the DC voltage whichis a negative value periodically becomes High/Low.

Modification 2

Next, descriptions will be made on a control method according toModification 2 of the embodiment with reference to FIG. 11. FIG. 11 is atiming chart illustrating the control method according to Modification 2of the embodiment.

For example, in the control method according to Modification 2, the LFpulse is applied to the stage 16 as illustrated in FIG. 11. The positivevalue of the LF pulse matches the positive peak of the LF voltage, andthe negative value of the LF pulse matches the negative peak of the LFvoltage.

In this case, in the control method according to Modification 2, thenegative DC voltage or the radio-frequency voltage periodically repeatsthe first state and the second state, the first state is applied in apartial time period within each period of the LF pulse, and the secondstate is applied continuously with the first state. With this controlmethod as well, the formation of a hole in an elliptical shape or theoccurrence of tiling at the edge of the wafer W may be prevented.

For example, in a portion of or entire LF pulse that is zero andpositive, the DC voltage may be controlled to the first voltage value ofthe first state, and in a portion of or entire LF pulse that isnegative, the second voltage value of the second state may be controlledto be larger than the first voltage value of the first state. Then,since the LF pulse is binarized, and accordingly, the DC voltage iscontrolled to be binarized, the control is facilitated.

Modifications 3-1 to 3-4

FIG. 12A is a timing chart illustrating a control method according toModification 3-1 of the embodiment. FIG. 12B is a timing chartillustrating a control method according to Modification 3-2 of theembodiment. FIG. 12C is a timing chart illustrating a control methodaccording to Modification 3-3 of the embodiment. FIG. 12D is a timingchart illustrating a control method according to Modification 3-4 of theembodiment. For example, in the control method according toModifications 3-1 and 3-2 illustrated in FIGS. 12A and 12B, the DCvoltage or the radio-frequency voltage is applied in a partial timeperiod when the periodically varying parameter that is the electrodepotential as an example includes a positive value, such that thepotential of the edge ring becomes the first state, and the second stateis applied continuously with the first state. In the control methodaccording to Modifications 3-3 and 3-4 illustrated in FIGS. 12C and 12D,the DC voltage or the radio-frequency voltage is applied in a partialtime period when the periodically varying parameter that is theelectrode potential as an example includes a negative value, such thatthe potential of the edge ring becomes the first state, and the secondstate is applied continuously with the first state. In Modifications 3-1illustrated in FIG. 12A and Modification 3-3 illustrated in FIG. 12C,the first state of the DC voltage has two or more first voltage valuesas negative values by stages. In this case as well, as for the negativeDC voltage, the first voltage value of the first state is smaller thanthe second voltage value of the second state.

When the radio-frequency voltage is applied, the absolute value of thefirst voltage value of the first state is larger than the absolute valueof the second voltage value of the second state. The radio-frequencyvoltage may be supplied from the second radio-frequency power supply 90to the edge ring 24, or an RF power supply may be separately provided toapply the radio-frequency voltage.

In Modification 3-2 illustrated in FIG. 12B and Modification 3-4illustrated in FIG. 12D, the first state of the radio-frequency voltagesmoothly has two or more first voltage values. In any case of FIGS. 12Aand 12B, the first state and the second state are periodically repeated.

For example, in Modification 3-1 illustrated in FIG. 12A andModification 3-3 illustrated in FIG. 12C, the first state of the DCvoltage has two or more first voltage values as negative values bystages. In this case as well, as for the negative DC voltage, the firstvoltage value of the first state is smaller than the second voltagevalue of the second state.

When the radio-frequency voltage is applied, the first voltage value ofthe first state is larger than the second voltage value of the secondstate. The radio-frequency voltage may be supplied from the secondradio-frequency power supply 90 to the edge ring 24, or an RF powersupply may be separately provided to apply the radio-frequency voltage.

In Modification 3-2 illustrated in FIG. 12B and Modification 3-4illustrated in FIG. 12D, the first state of the radio-frequency voltagesmoothly has two or more first voltage values. In any case of FIGS. 12Ato 12D, the first state and the second state are periodically repeated.

As described above, the negative DC voltage or the radio-frequencyvoltage periodically repeats the first state and the second state. Forthe negative DC voltage, the first voltage value of the first state issmaller than the second voltage value of the second state, and for theradio-frequency voltage, the first voltage value of the first state islarger than the second voltage value of the second state.

The first state of the DC voltage or the radio-frequency voltage may beapplied in a partial time period when the electrode potential includes anegative value. In Modifications 3-1 and 3-2, the DC voltage or the RFvoltage is controlled to multiple values in the first state, so that theformation of a hole in an elliptical shape or the occurrence of tiltingat the edge of the wafer W may be prevented. In addition, the DC voltageand the RF voltage in the first state according to each modification maybe values corrected according to the degree of consumption of the edgering 24.

The frequency of the RF voltage supplied to the edge ring 24 may behigher than the frequency of the bias power. Descriptions will be madeon an appropriate value of the frequency of RF when the RF voltage isapplied to the edge ring 24 with reference to FIGS. 13, 14A, 14B, and15A to 15C. FIGS. 13, 14A, 14B, and 15A to 15C are views illustrating anexample of the frequency of RF and the potential difference between thewafer W and the edge ring 24 according to the embodiment.

As illustrated as an example in FIG. 13, when an RF voltage with a lowerfrequency (200 kHz) than the frequency of the bias power (400 kHz) isapplied to the edge ring 24, various potential differences occur betweenthe potential of the wafer W and the potential of the edge ring 24, andaccordingly, the sheath thickness of the wafer W and the sheaththickness of the edge ring 24 vary largely in the radial direction.Thus, when the RF voltage with the frequency lower than the frequency ofthe bias power is applied to the edge ring 24, the etching shape in thevicinity of the edge of the wafer W may be deteriorated.

Next, descriptions will be made on a case where an RF voltage with thesame frequency as the frequency of the bias power (400 kHz) is appliedto the edge ring 24 as illustrated in FIGS. 14A and 14B. FIG. 14Arepresents the potential of the wafer W and the potential of the edgering 24 in a case where the RF voltage is changed by making the phase ofthe RF voltage equal to the phase of the bias power. In this case, therelationship in size of sheath thickness between the wafer W and theedge ring 24 may not be changed. For example, while the potential of theedge ring 24 may be made deep, the sheath of the edge ring 24 may not bemade thin.

FIG. 14B represents the potential of the wafer W and the potential ofthe edge ring 24 in a case where the phase of the RF voltage is changedwith respect to the phase of the bias power. In this case, in the regionT of FIG. 14B, the potential of the wafer W becomes deeper than thepotential of the edge ring 24, and the sheath of the edge ring 24becomes thinner than the sheath of the wafer W. Meanwhile, in the regionU of FIG. 14B, the potential of the edge ring 24 becomes deeper than thepotential of the wafer W, and the sheath of the edge ring 24 becomesthicker than the sheath of the wafer W. Hence, the incidence angle ofions in the vicinity of the edge of the wafer W may be directed inwardor outward according to the potential difference between the potentialof the wafer W and the potential of the edge ring 24. Thus, theroundness of a hole in the vicinity of the edge of the wafer W maycollapse. Accordingly, when the RF voltage with the same frequency asthat of the bias power is applied to the edge ring 24, it is preferableto align the phases of LF and RF.

FIGS. 15A to 15C are views in which the application time of the RFvoltage is adjusted in a case where the RF voltage with a frequencyhigher than the frequency of the bias power is applied to the edge ring24. FIG. 15A represents the amplitude of the bias power and theamplitude of the RF voltage in a case where the RF voltage is appliedwhen the wafer potential (which is substantially equal to the electrodepotential) in which Vdc of LF is deep and Vpp is large is negative.

FIG. 15B represents the amplitude of the bias power and the amplitude ofRF in a case where the RF voltage is continuously applied. FIG. 15Crepresents the amplitude of the bias power and the amplitude of RF in acase where the RF voltage is applied when the wafer potential ispositive.

In FIG. 15A, the RF voltage is applied to the edge ring 24 at a timingwhen Vdc of LF is deep and Vpp is large. When the electrode potential isnegative, the plasma density decreases, and the sheath of the edge ring24 becomes thick. Accordingly, the incidence angle of ions in thevicinity of the edge of the wafer W may be corrected to be vertical orbe directed radially outward.

Meanwhile, in FIG. 15C, when the electrode potential is positive, theplasma density increases, and the sheath of the edge ring 24 becomesthin. Accordingly, the incidence angle of ions in the vicinity of theedge of the wafer W may be corrected to be vertical or directed radiallyinward.

From the above, the thickness of sheath of the edge ring 24 may becontrolled by continuously applying the RF voltage as illustrated inFIG. 15B or intermittently applying the RF voltage according to thevalue of the electrode potential as illustrated in FIGS. 15A and 15C. Asa result, the etching shape in the vicinity of the edge of the wafer Wmay become favorable.

Descriptions have been made on the method of controlling the DC voltageto be applied to the edge ring 24 from the variable DC power supply 50.However, the present disclosure is not limited thereto, and for example,the radio-frequency voltage to be applied to the edge ring 24 from an ACpower supply (not illustrated) may also be controlled in the same manneras the method of controlling the DC voltage.

That is, the plasma processing apparatus according to the presentembodiment may include; a processing container; an electrode configuredto place a workpiece thereon in the processing container; a plasmageneration source configured to supply plasma into the processingcontainer; a bias power supply configured to supply a bias power to theelectrode; an edge ring disposed at a periphery of the workpiece; aradio-frequency power supply configured to supply a radio-frequencyvoltage having the same frequency as a frequency of the bias power tothe edge ring; a storage medium having a program that includes a firstcontrol procedure of applying the radio-frequency voltage to generate apredetermined phase difference with respect to a phase of a potential ofthe electrode; and a controller configured to execute the program of thestorage medium. The predetermined phase difference may be 90° to 270°.

In addition, for example, a voltage obtained by combining the DC voltagewith another voltage, for example, combining the DC voltage with avoltage output in a triangular wave may be applied.

The program may be set at a predetermined position in a state of beingstored in a portable computer-readable storage medium such as a CD-ROMor a DVD, and may be read out by the controller.

Modification 4

Modification 4 will be described with reference to FIG. 16. FIG. 16 is atiming chart illustrating a control method according to Modification 4of the embodiment. In Modification 4, the first state of the DC voltagetakes a pulse type voltage value in which two or more voltage values arerepeated. In the example of FIG. 16, the first state of the DC voltagerepeats a negative voltage value and a zero voltage value. However, thepresent disclosure is not limited thereto, and two or more voltagevalues, for example, three voltage values may be repeated.

Modification 5

Modification 5 will be described with reference to FIG. 17. FIG. 17 is atiming chart illustrating a control method according to Modification 5of the embodiment. The bias power may be a power of a sine waveform, apulse waveform, or a tailored waveform. That is, the bias voltage orcurrent may be a sine waveform or an LF pulse waveform. The LF pulseincludes an arbitrary waveform such as the tailored waveform illustratedin FIG. 17, in addition to the waveform illustrated in FIG. 11. In thetailored waveform, the bias power may be modulated when the DC voltageillustrated in FIG. 17 is in the second state or in the first state.

Similarly, when the first state of the DC voltage takes two or morevoltage values, in the waveform of the DC voltage, the first state maytake two or more voltage values, and the second state may take two ormore voltage values as illustrated in FIGS. 12A to 12D. The voltagevalue of the second state may be zero. In addition, as illustrated inFIG. 16, the first state may repeat two or more voltage values. Thewaveform of the first or second state of the DC voltage may be thetailored waveform illustrated in FIG. 17, similarly to the LF pulse.

As described above, the potential of the electrode may be determined bythe periodically varying parameter measured in the transmission path ofthe bias power. The periodically changing parameter may be a variance ofa voltage, current, electromagnetic field, light emission of generatedplasma, or sheath thickness above the workpiece. The potential of theelectrode may be determined by a signal synchronized with the period ofthe radio-frequency or pulse wave of the bias power.

The plasma processing apparatus according to the present disclosure maybe applied to any type of capacitively coupled plasma (CCP), inductivelycoupled plasma (ICP), a radial line slot antenna (RLSA), electroncyclotron resonance plasma (ECR), and helicon wave plasma (HWP).

In the descriptions herein, the semiconductor wafer W has been describedas an example of the workpiece. However, the workpiece may not belimited thereto and may be, for example, various substrates used in aliquid crystal display (LCD) and a flat panel display (FPD), a CDsubstrate or a printed circuit board.

According to an aspect, it is possible to improve the precision of theetching shape of the workpiece.

From the foregoing, it will be appreciated that various embodiments ofthe present disclosure have been described herein for purposes ofillustration, and that various modifications may be made withoutdeparting from the scope and spirit of the present disclosure.Accordingly, the various embodiments disclosed herein are not intendedto be limiting, with the true scope and spirit being indicated by thefollowing claims.

What is claimed is:
 1. A plasma processing apparatus comprising: aprocessing container; an electrode configured to place a workpiecethereon in the processing container; a plasma generation sourceconfigured to supply plasma into the processing container; a bias powersupply configured to supply a bias power to the electrode; an edge ringdisposed at a periphery of the workpiece; a DC power supply configuredto supply a DC voltage to the edge ring; and a controller configured toexecute a first control procedure in which the DC voltage periodicallyrepeats a first state having a first voltage value and a second statehaving a second voltage value higher than the first voltage value, thefirst voltage value is supplied in a partial time period within eachperiod of a potential of the electrode, and the second voltage value issupplied such that the first state and the second state are continuous.2. The plasma processing apparatus according to claim 1, wherein thepotential of the electrode is determined by a periodically varyingparameter measured in a transmission path of the bias power or a signalsynchronized with a period of a radio-frequency or pulse wave of thebias power, and the periodically varying parameter is a voltage, acurrent, an electromagnetic field, a variance of light emission ofgenerated plasma, or a variance of a sheath thickness of plasma abovethe workpiece.
 3. The plasma processing apparatus according to claim 1,wherein the partial time period includes a timing when the potential ofthe electrode becomes a positive peak.
 4. The plasma processingapparatus according to claim 1, wherein the controller executes a secondcontrol procedure of intermittently stopping the DC voltage in anindependent period from the potential of the electrode.
 5. The plasmaprocessing apparatus according to claim 1, wherein the controllerexecutes a third control procedure of intermittently stopping the biaspower in an independent period from the period of the DC voltage.
 6. Theplasma processing apparatus according to claim 1, wherein the controllerexecutes a second control procedure of intermittently stopping the DCvoltage in an independent period from a period of the periodicallyvarying parameter, and a third control procedure of intermittentlystopping the bias power in the independent period from the period of theDC voltage in synchronization with the second control procedure.
 7. Theplasma processing apparatus according to claim 1, wherein the firststate takes two or more voltage values.
 8. The plasma processingapparatus according to claim 7, wherein the first state repeats the twoor more voltage values.
 9. The plasma processing apparatus according toclaim 1, wherein the second state takes two or more voltage values. 10.The plasma processing apparatus according to claim 1, wherein a voltagevalue of the second state is zero.
 11. The plasma processing apparatusaccording to claim 1, wherein the first voltage value is correctedaccording to a degree of consumption of the edge ring.
 12. A plasmaprocessing apparatus comprising: a processing container; an electrodeconfigured to place a workpiece thereon in the processing container; aplasma generation source configured to supply plasma into the processingcontainer; a bias power supply configured to supply a bias power to theelectrode; an edge ring disposed at a periphery of the workpiece; aradio-frequency power supply configured to supply a radio-frequencyvoltage having a same frequency as a frequency of a voltage of the biaspower to the edge ring; and a controller configured to execute a firstcontrol procedure of applying the radio-frequency voltage to generate apredetermined phase difference with respect to a phase of a potential ofthe electrode.
 13. The plasma processing apparatus according to claim12, wherein the controller executes a second control procedure ofintermittently stopping the radio-frequency voltage in an independentperiod from the potential of the electrode.
 14. The plasma processingapparatus according to claim 12, wherein the controller executes a thirdcontrol procedure of intermittently stopping the bias power in anindependent period from the period of the radio-frequency voltage. 15.The plasma processing apparatus according to claim 12, wherein thecontroller executes a second control procedure of intermittentlystopping the radio-frequency voltage in the independent period from thepotential of the electrode, and a third control procedure ofintermittently stopping the bias power in the independent period fromthe period of the radio-frequency voltage in synchronization with thesecond control procedure.
 16. The plasma processing apparatus accordingto claim 12, wherein the predetermined phase difference is 90° to 270°.17. A method of controlling a plasma processing apparatus that includes:a processing container; an electrode configured to place a workpiecethereon in the processing container; a plasma generation sourceconfigured to supply plasma into the processing container; a bias powersupply configured to supply a bias power to the electrode; an edge ringdisposed at a periphery of the workpiece; and a power supply configuredto supply a DC voltage to the edge ring or a radio-frequency voltagehaving a same frequency as a frequency of a voltage of the bias power tothe edge ring, the method comprising: when the power supply supplies theDC voltage, controlling the DC voltage such that a first state having afirst voltage value and a second state having a second voltage valuehigher than the first voltage value are periodically repeated, andapplying the first voltage value in a partial time period within eachperiod of the potential of the electrode, and applying the secondvoltage value such that the first state and the second state arecontinuous, and when the power supply supplies the radio-frequencyvoltage, applying the radio-frequency voltage such that a predeterminedphase difference is generated with respect to a phase of a potential ofthe electrode.
 18. The method according to claim 17, further comprising:generating a synchronization signal to be synchronized with thepotential of the electrode, generating a control signal for the DC powersupply that is output from the synchronization signal, and transmittingthe generated control signal to at least one of the DC power supply anda phase shift circuit, and supplying a DC voltage to the edge ring fromat least one of the DC power supply and the phase shift circuit.
 19. Themethod according to claim 17, further comprising: generating a controlsignal for the radio-frequency voltage that is output from the biaspower supply, and transmitting the generated control signal to a phaseshift circuit; and supplying the radio-frequency voltage to the edgering from the phase shift circuit.